1. Field of the Invention
The invention relates to an output circuit, and more particularly to an output circuit with electrostatic discharge protection.
2. Description of the Related Art
Electrostatic discharge (ESD) damage has become one of the main reliability concerns facing integrated circuit (IC) products. Generally, an output circuit of a power stage in an IC comprises a PMOS transistor and an NMOS transistor which are coupled to an output terminal of the power stage. During a manufacture process or a product test process, when an ESD event occurs at the output terminal, a large current may damage elements of the power stage. Thus, an ESD prevention circuit is required to provide a discharging path when an ESD event occurs at the output terminal. In prior arts, an ESD prevention circuit is coupled to an output terminal of a power stage in an IC for providing ESD prevention when an ESD even occurs at the output terminal. However, the ESD prevention circuit occupies a large area in the IC. Moreover, when the ESD prevention circuit is desired to have high reliable, the design of the ESD prevention circuit becomes difficult.